APPARATUS AND METHOD FOR MULTIPROCESSOR SYSTEM INCLUDING QUASI-STATIC ARCHITECTURE AND SCHEDULING

A parallel processing architecture centralized controller for containing a granting access to a shared resource for a plurality of processors by use of a transaction schedule. The controller includes a memory for storing a schedule, a pointer into the memory for accessing a particular entry in the schedule, a control circuit for asserting a grant signal to a particular one processor according to the entry in the schedule which the pointer identifies, and an incrementer for advancing the pointer to the next schedule entry upon an assertion of a release signal from the processor granted access to a shared resource. A particular processor accesses the shared resource only when its grant signal is asserted, therefore the controller imposes a particular order on the transaction of the plurality of processors and allows some execution time variations from those execution times which a compiler used in establishing the schedule. The parallel processing architecture includes a shared resource coupling the processor to allow transactions among the processors. Variations in the controller allow monitoring of the shared resource to determine decision paths and to use appropriate portions of the transaction schedule depending upon a particular decision path.