Patent US 5,377,345

Apparatus and methods for a cache controller preserving cache consistency and providing multiple outstanding operations in a cache memory structure supporting a high performance central processor unit (CPU). An external cache array is coupled to both the CPU and a cache controller (CC), and is subblocked to reduce miss rate. The CC is coupled via a high speed bus to a main memory. A cache directory in the CC tracks usage of the external cache, and is organized to support a choice of bus protocols for buses intercoupling the CC to the main memory. The cache directory consists of tag entries, each tag entry having an address field and multiple status bit fields, one status bit field for each subblock. The status bit fields, in addition to shared-, owner-, and valid-bits, have a pending-bit which, when set, indicates a pending uncompleted outstanding operation on a subblock, and will prevent the CPU from overwriting the corresponding subblock. Two block miss registers in the CPU aid in prefetching subsequent subblocks upon subblock miss. The block miss registers further identify operations known to be pending but not particularly identified by the set pending-bit. One block miss register identifies a miss upon read, whereas the other block miss register identifies a miss upon write. An I/O count register in the CC tracks the number of I/O write operations outstanding but not yet completed, and prevents saturation of the I/O bus and buffer space. All outstanding write operations may be tracked with a single register. The CC also supports a PEND signal sent from the CC to the CPU to inform the CPU there exist outstanding write operations, to maintain store ordering in a multiple processor environment.