RADAR PROCESSING APPARATUS AND METHOD

A radar processor comprises a multi-port memory device having memory which can be accessed by at least three ports. A first port receives input data from a data providing means. A second port couples a first processor which performs radar processing. A third port couples at least one second processor which assists the first processor by also performing radar processing. The multi-port memory device further includes an arbiter for coordinating and determining when each of the three ports can access the memory of the multi-port memory device. The first and second processors share information with each other via the multi-port memory device.