SYSTEM AND METHOD FOR REDUCING THE PENALTY ASSOCIATED WITH DATA CACHE MISSES

A computer system having a central processor unit (CPU) with a reduced instruction set, a decoder and a data cache memory, for processing an instruction to retrieve data from a main memory to prevent a data cache miss. The system decodes an instruction requiring the CPU to load a value into a read only general purpose memory register, the instruction thereby indicating to the CPU to perform a prefetch operation and providing information corresponding to an address of the data to be fetched from the main memory. The system processes, substantially simultaneously, further instructions following the load register instruction and the prefetch operation by determining the address in main memory of the data to be prefetched using the information provided by the load instruction, fetching the data from the main memory, and storing the data in the data cache memory to permit accesses to the data and thereby reduce the penalty associated with a data cache miss.