Patent US 5,410,550

An asynchronous latch circuit characterized by a pair of D-type flip-flops and a D-type latch. Data is clocked into a first flip-flop by a system clock signal and the output of the first flip-flop is clocked into a second flip-flop by an asynchronous latch enable signal. A comparator compares the outputs of the first and second flip-flops and develops an error signal if the two are not the same. The error signal forces the output of the latch to a known condition rather than letting the output be indeterminate. In an asynchronous latch register an error signal from any one of the asynchronous latch circuits will force all of the latch circuits in the register to a known condition to eliminate race condition errors.