TEST PATTERN GENERATING APPARATUS

A test pattern generating apparatus for generating test patterns to test a sequential circuit having at least one memory element. The apparatus calculates, in response to a primary input applied to the sequential circuit, analog logic values for signal lines in the sequential circuit using a nonlinear function, then stores history data for the analog logic values with an inverse covariance matrix of the analog logic values. The apparatus then calculates an evaluation value according to the degree of variance between the analog logic values and the history data. A primary input setting unit is used for producing a next primary input which provides a maximum evaluation value from the evaluation value obtained from the present primary input. inputs produced by the primary input setting unit.