Patent US 5,437,049

A reduction processor controlled by a program having a structure reduces the structure in a number of reduction steps implementing different kinds of reduction operations. A first order processor of this kind includes an active storage (1, 2) which in turn includes a number of active storage cells, each able to store information which could give rise to a reduction. A communication net communicates the result of each reduction to all cells having connection to the result. The processor includes a control unit in common for all the storage cells. Preferably, at least one of the storage cells, called core cell or structure arithmetic unit, is able to perform all kinds of reductions, and the rest of the cells, called object storage cells, are able to perform only limited number of reductions. Further, several reduction processors could be connected to each other by a network and thereby form a higher order reduction processor.