COUNTER MALFUNCTION DETECTION USING PRIOR, CURRENT AND PREDICTED PARITY

A counter system having associated counter error detection circuitry that utilizes the current parity, the previous parity, and a predicted parity for evaluating counter operation is described. In successive count cycles, a predicted parity is utilized, during the next subsequent count cycle is stored in flip-flop as the current parity, and in the next subsequent count cycle is stored a second flip-flop as a previous parity. Circuit are described for performing parity check and parity prediction functions. The previous parity, current parity and predicted parity will not be alike for any binary counter that operates properly. Circuity is described that holds and compares the parity of the Count, the current parity, and the previous parity, during each counter advance cycle and to provide an error signal when the counter is detected to be stuck.