CLOCK CONTROL FOR POWER SAVINGS IN HIGH PERFORMANCE CENTRAL PROCESSING UNITS

The invention relates to a clock controller circuit for performing a power saving feature in high performance microprocessors. The invention utilizes two logic gates and a flip flop for disabling a clock signal to an execution unit or ALU when data is not available for the execution unit or ALU. The invention provides a sleep mode or clock idle mode for an execution unit when data is not available for the execution unit because memory units, I/O devices, or internal caches are unable to provide data or instructions to the execution unit. The clock controller circuit disables the clock signals by gating the clock signal to a logic high. The clock controller circuit stops the clock signals in response to a no data available signal from a bus unit and a data required signal from the execution unit.