Patent №
US 5,453,583
Granted
1995-09-26
Filed 1993
Owner
LSI LOGIC CORPORATION
Lab
—
AI components
1
vision
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
08058117
A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping the bond pads into a relatively small (compared to the total area of the die) sub-area within an interior area (generally away from the periphery) of the die. By keeping the bond pad layout small (tightly grouped, or oriented along a single row, or axis), differential thermally induced displacements between the bond pads are minimized, or are controlled in one dimension. Further, the bond pads may be disposed in a small area near the center of thermal expansion (centroid) of the die or near a heat-producing circuit element to minimize absolute thermal displacements of individual bond pads from the centroid or the circuit element. Overlapping sub-area patterns may be used, and grouped bond pads may be used in conjunction with (including overlapping of) traditional die-periphery located bond pads. Other aspects involve disposing the bond pads into an elongated pattern to minimize thermal displacement primarily in one direction, and orienting a lead frame or the like to accommodate any thermal migration of the bond pads in a controlled direction.
AI classification
Ownership
LSI LOGIC CORPORATION
assignment · 65060580
Assignors
ROSTOKER, MICHAEL D., PASCH, NICHOLAS F., ZELAYETA, JOE
On an employer assignment, the assignors are typically the inventors.