APPARATUS FOR FURNISHING INSTRUCTIONS IN A MICROPROCESSOR WITH A MULTI - STAGE PIPELINE PROCESSING UNIT FOR PROCESSING INSTRUCTION PHASE AND HAVING A MEMORY AND AT LEAST THREE ADDITIONAL MEMORY UNITS

An apparatus for furnishing instructions having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, includes a memory; an address register having contents pointing to an instruction to be processed in said memory; an instruction register for receiving a loading of the instruction during an instruction loading phase; an arithmetic calculation unit for calculating addresses; an incrementing stage for incrementing the contents of said address register; and a multiplexer for selecting a calculated address or an incremented successor address. One embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit. Another embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit.