Patent US 5,457,788

An associative memory system using an associative memory circuit, capable of performing hit judgment on cache data at a high speed. The associative memory system comprises a virtual-address holding CAM circuit 2 for outputting a hit signal 5 when the data previously stored in a supplied address coincides with a supplied virtual address 4, a cache-tag memory circuit 1 for outputting cache-tag data coinciding with the supplied virtual address 4 when the data is present, and a physical-address holding CAM circuit 3 which connects with an output line for outputting the hit signal 5 given from the CAM circuit 2 and outputs the hit signal 6 when a physical address previously stored in the memory area from which the hit signal is outputted coincides with cache tag data supplied from the cache-tag memory circuit 1.