PROGRAM COUNTER MECHANISM HAVING SELECTOR FOR SELECTING UP-TO-DATE INSTRUCTION PREFETCH ADDRESS BASED UPON CARRY SIGNAL OF ADDER WHICH ADDS INSTRUCTION SIZE AND LSB PORTION OF ADDRESS REGISTER

A program counter for a prefetch mechanism in a stored program arithmetic unit for generating an instruction address of an immediately succeeding instruction by using a portion of or the entire prefetch address and a current instruction address, includes a prefetch address generator and an instruction address generator. The prefetch address generator includes a first n-bit register storing a current prefetch address, an n-bit adder for obtaining a next prefetch address, and a first n-bit selector. The instruction address generator includes a second n-bit register storing a current instruction address, an m-bit adder, an (n-m)-bit selector and a second n-bit selector.