MULTIPLYING CIRCUIT AND MICROCOMPUTER INCLUDING THE SAME

A multiplying circuit wherein an adder 7 outputs a value "0" in which both of a positive part and a negative part of a number with a redundant code are "1", and at a last cycle of the multiplication cycles, the finish detecting circuit 13 detects finishing of multiplication cycles by detecting that "1" exists in a portion storing a positive part of a number with a redundant code of the third bit from the lowest bit of the second latch 8 and in a portion storing a negative part of the same at the same time. In such a construction, a counter circuit for counting multiplication cycles according to the Booth algorithm utilizing a number with a redundant code can be omitted. Accordingly, the number of transistors is reduced and the circuit configuration becomes simple.