HIGH SPEED PATTERN RECOGNITION TECHNIQUE FOR IMPLEMENTATION OF RESOLUTION ENHANCEMENT ALGORITHMS INTO AN APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC) DEVICE

A circuit to be used just prior to the printing engine to improve the image quality of a raster output scanner by modifying the darkness, size or shape of the spot. A buffer holds a window of n by n image pixels, and compares the bit pattern to a set of templates. For each match, a correction number is output, each correction number being a gray scale, duty cycle or bit pattern to be used to correct the center pixel of the current window. The comparison logic, instead of comparing the entire set of bits in the window to the templates, uses a number of small logic blocks in parallel, each comparing a subset of bits from the window. The output from this first set of comparisons is substantially reduced from the original set. This reduced set is now input to a second logic block which generates the final correction output bits. By using two stages, the first stage being a number of smaller logic blocks, the speed of the process is increased and the number of parts and the complexity of the circuit is reduced