MICROCOMPUTER WITH TEST MODE SWITCHING FUNCTION

A microcomputer provided with test mode switching function includes an execution control unit to control the operation of an operation unit, an bus control unit connected via an internal bus to the operation unit and the execution control unit and a test mode control unit to control the switching to the test mode. The execution control unit has a micro address generating unit capable of generating a particular address to execute a microinstruction which separates the operation unit from the internal bus according to a test mode specification signal from the test mode control unit. Alternatively, the execution control unit has an instruction register capable of outputting, to the micro address generating unit, the instruction code of the microinstruction which separates the operation unit from the internal bus.