INTEGRATED CIRCUIT MEMORY WITH DISABLED EDGE TRANSITION PULSE GENERATION DURING SPECIAL TEST MODE

An integrated memory circuit having special stress test mode capability, and that is safely controlled by edge transition detection, is disclosed. The memory includes a test mode enable circuit that generates a test mode enable signal responsive to receiving overvoltage signals or other codes at terminals of the memory; the test mode enable signal is presented to the edge transition detection circuitry, so that the edge transition detection pulse that would otherwise initiate a memory operation is not generated during special test mode. This prevents the disastrous possibility that memory functions would be initiated by false edge transition detection signals (such as may occur during ramping of supply voltages to stress levels) during the special test mode. Special tests, such as stress tests and long write cycle disturb tests, may thus be safely performed.