Patent US 5,504,872

A multiprocessor system address translation register control device that creates a directory for the handling of various address translation registers, wherein the directory retains processor data indicative of which of a plurality of address translation registers that can be accessed by multiple processors are actually being used by those processors. This device also uses a partial number register for the handling of various address translation registers, wherein the partial space number register retains partial space numbers for the partial space that all of the address translation registers take as input. By setting and resetting processor indicating data numbers to this directory, and by setting partial space numbers to a partial space number register, this device controls the address translation register allotments for the handling of multiple processors.