OUTPUT CIRCUIT FOR AN TTL-CMOS INTEGRATED CIRCUIT

An output circuit for a TTL-CMOS integrated circuit that comprises an output stage with two P MOS and N MOS transistors in parallel, which are connected in cascade with an N MOS enabling transistor between the power supply and the reference voltages. The output stage connected by means of a validation signal TRISB and of P and N MOS transistors delivers an output signal representing the input logic variable to the common point between the P MOS transistor and enabling transistor. A first circuit allows switching of the P MOS transistor by an intermediate switching control signal TRISP and a third circuit allows switching of the N MOS transistor, the circuit operating in mode of feedback of the switching control of the P MOS transistor, the controls being applied successively in order to generate an intermediate switching level belonging to the high logic level.