Patent US 5,564,029

The present invention discloses a pipeline processor system comprising a pipeline processor and a memory device, wherein the memory device is comprised of a memory unit for holding data and/or an instruction as well as being accessed to implement memory read operation or memory write operation in a clock cycle; and a data latch unit for latching data to be written into the memory unit, while the pipeline processor is comprised of an instruction detection unit for detecting from fetched instructions a first predetermined instruction which directs the latch of the data as well as a second predetermined instruction which directs write of the data at the data latch means into the memory means; and a latch control unit for controlling to latch operation results of the first predetermined instruction to the data latch unit when the predetermined instruction is detected by the instruction detection unit as well as controlling to write the data at the data latch unit into the memory unit when the second predetermined instruction is detected. The first predetermined instruction includes operand fetch from the memory unit replaced with the latch of the operand, the operand fetch encompassing two memory accesses having been planned in a clock cycle together with the memory write operation; and the second predetermined instruction includes execution of an instruction and the write of the data at the data latch means into the memory means, the instruction placing after the first predetermined instruction and excluding its own memory access.