HIGH SPEED, LOW POWER PIPELINED LOGIC CIRCUIT

A complementary pipelined logic circuit includes (a) a logic unit that processes a plurality of complementary inputs into a pair of complementary outputs, (b) a load circuit that is connected to a voltage supply node to establish complementary outputs having a voltage swing greater than the output voltage swing of the logic unit, and (c) a control circuit that interfaces between the logic unit and the load circuit and responds to a clock input by controlling the logic state of the load circuit's outputs in accordance with the logic state of the logic unit's outputs. The load circuit is preferably implemented as a regenerative latching circuit that pulls the output voltage swing up to the full supply voltage value. The logic unit and control circuit are preferably implemented with N-channel devices for high speed and compactness, while the latching load circuit is preferably implemented with P-channel devices to obtain a full scale voltage pullup.