SYSTEM FOR MODELING AN INTEGRATED CHIP PACKAGE AND METHOD OF OPERATION

A system for modeling an integrated chip package and a method of operation is disclosed that includes a parametric processor (1) that provides parameters to define the parts of the package to a volume generator (2). The volume generator (2) uses the parameters to create volumes associated with each part of the integrated chip package. The system (3) provides the volume coordinates to a mesh generator (4). The mesh generator (4) further subdivides the volumes into elements, the elements being small enough for use in finite element analysis. The output of the mesh generator (4) is provided to a finite element analysis processor (5). The finite element analysis processor (5) conducts a physical stress or thermal stress analysis on the package using the elements created by the mesh generator (4). Once the finite element analysis processor (5) has completed its analysis of the package, the result is displayed on a display (6).