Patent №
US 5,604,680
Granted
1997-02-18
Filed 1994
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
08290364
A method and system provide for the symbolic design of a symbolic layout of an integrated circuit using only the topological features of the cells of the layout, absent geometrical information. Virtual leaf cells define circuit elements, and virtual hierarchical cells combine virtual leaf cells and other virtual hierarchical cells into hierarchical arrangements using interface graphs. Virtual interfaces describe the connectivity and orientation relations between virtual cells. The interfaces inherit the definitional requirements of interfaces at lower levels. The symbolic layout is produced from a hierarchy of virtual cells using hierarchical compaction and routing technology.
AI classification
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 71200394
Assignors
BAMJI, CYRUS, VARADARAJAN, RAVI
On an employer assignment, the assignors are typically the inventors.