Patent US 5,625,834

In an information processing system of the present invention, a vector processor has a plurality of vector pipeline sets operable under control of an instruction controller. The vector pipeline sets are operable in a parallel mode or in an individual mode with reference to an operation mode flag kept in a mode flag register. The instruction controller includes a plurality of vector instruction control units which correspond to the respective vector pipeline sets and which monitor states of the vector instruction control units to detect whether or not an error has taken place in each of the vector instruction control units. The vector pipeline sets are connected to a vector data memory through a pipeline crossbar switch to fetch a common data signal from the vector data memory on demand.