PROCESSOR HAVING MULTIPLE INSTRUCTION REGISTERS

A program is stored alternately in the memories 1A and 1B one word at a time. One execution circuit 5 is induced to select and execute the outputs of instruction decoders 4A and 4B alternately. After the execution circuit 5 holds the output of the instruction decoder 4A (4B), the instruction decoder 4A (4B) is induced to decode the output of the instruction register 3A (3B), a program counter 2A (2B) is induced to update the output and a instruction register 3A (3B) is induced to hold the output of the memory 1A (1B).