BUS DEADLOCK PREVENTION CIRCUIT FOR USE WITH SECOND LEVEL CACHE CONTROLLER

A computer system which corrects errors in a second level cache controller. The cache controller erroneously provides the cycle lock signal for the entire period of a writeback cycle followed by an I/O bus access, thus causing a deadlock if an I/O bus master needs access to the host bus at the same time. A circuit determines when the writeback cycle is occurring and masks the lock signal during the writeback operation, so that the long lock assertion is not present and the arbiters can properly control the access to the buses.