SIGNAL PROCESSOR WITH DELAY LINE MANAGEMENT LOGIC

A processing system includes delay line management logic that automatically clears the delay lines without actually filling the delay line memory with zeroes. The processing system comprises a signal processor that executes programs using delay lines. A memory, coupled to the signal processor, includes a set of memory locations to store the delay lines. Delay line management logic is responsive to a command to automatically clear for the programs being executed by the signal processor a subset of the set of memory locations allocated to a particular delay line without writing to the subset of memory locations. The delay line management logic includes a register file to store parameters for the delay lines. The parameters for particular delay lines include an offset within the set of memory locations pointing to the subset of memory locations allocated to the particular delay line, and a count indicating the number of valid memory locations in the subset. The command to clear the delay line comprises an operation to update the register file by, for instance, setting the count for the particular delay line to zero.