REPEATER FOR A DIGITAL COMMUNICATION SYSTEM WHICH ELIMINATES CUMULATIVE JITTER

An electronic repeater for a digital communication system which eliminates cumulative jitter is comprised of an input terminal on which a continuous input series of bits is received, at a repeater input bit rate. This input series of bits constitute an interleaved bit-serial sequence of input headers and data blocks. Also, the repeater includes an output terminal on which a continuous output series of bits are transmitted, at a repeater output bit rate that is not equal to and is independent of the repeater input bit rate. This output series of bits constitute an interleaved bit-serial sequence of output headers and the received data blocks. Further the repeater includes a digital logic circuit, coupled between the input terminal and the output terminal, which generates the output headers by occasionally adding bits to/subtracting bits from the input headers, such that a count of the number of bits added minus the number of bits subtracted plus the number of bits received minus the number of bits transmitted stays within a predetermined range.