Patent №
US 5,731,983
Granted
1998-03-24
Filed 1995
Owner
NEC USA, INC.
Lab
—
AI components
1
kr
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
08581417
A method of circuit synthesis which considers all circuit configurations that can be designed utilizing a retiming with logic duplication (RLD) methodology. These circuit configurations (RLD configurations) each have significantly different area, performance and testability characteristics and are represented as a set of feasible solutions to an integer linear program (ILP). The ILP permits the evaluation of different design and testability metrics for each of the configurations. An approach to solve several useful special cases of the ILP in polynomial time and an application of RLD transformation to partial scan is shown. Using this method, a desired RLD configuration is produced having a minimal number of duplicated logic nodes.
AI classification
Ownership
NEC USA, INC.
assignment · 78910225
Assignors
BALAKRISHNAN, ARUNKUMAR, CHAKRADHAR, SRIMAT T.
On an employer assignment, the assignors are typically the inventors.