Patent US 5,740,459

A data sorting circuit comprising: a data bus 1 for sequentially transmitting data to be sorted; a plurality of cascaded data registers (GR) for storing data in magnitude order, each of the data registers being initialized to a predetermined initial value; and a plurality of data transferring means (GS) each associatively provided for each of the data registers respectively, the data transferring means executing one of the following three operations: storing operation which transfers data appearing on the data bus to the associated data register; shifting operation which transfers data stored in the preceding data register to the associated data register; and no operation which does not transfer any data. The data sorting circuit further comprises: a plurality of transfer control circuits (31, 32, 33) each associatively provided for each of the data transferring means respectively, each of the transfer control circuits controlling the operation of the associated data transferring means.