Patent US 5,754,869

A system for managing power consumption in a personal computer, specifically the CPU and on-board system devices. The present invention manages the power consumption of the CPU and on-board system devices (i.e., core logic) using a global event messaging scheme and an OS-Idle power event and interrupts to provide CPU power management. The CPU's low-power state is implemented such that any or a set of predetermined device interrupts will transition the CPU from low-power state to normal operation which commences at the first instruction of the interrupt handler invoked by the device interrupt. The power consumed by the platform/chipset and controller logic devices, i.e., core logic, influenced by system clocks can be managed by decreasing frequency or stopping the distributed clock(s) altogether when in low-power state. Where chipsets manage clock distribution, additional hardware mechanisms for curtailing clocks may be incorporated which can be activated by software but are de-activated automatically in hardware. A power management coordinator may be incorporated to reduce voltage spikes or sags.