NTRUCTURE AND METHOD TO PREVENT OVER ERASURE OF NONVOLATILE MEMORY TRANSISTORS

Patent №

US 5,774,400

Granted

1998-06-30

Filed 1996

Owner

NVX CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

08772970

A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.

AI hardwareG11C 16/3477G11C 16/14G11C 16/3468

AI classification

AI hardware0.87
Planning0.01
Natural language0.00
Machine learning0.00
Evolutionary computation0.00
Knowledge representation0.00
Speech0.00
Vision0.00

Ownership

NVX CORPORATION

assignment · 83600785

Assignors

LANCASTER, LOREN T., HIROSE, RYAN T.

On an employer assignment, the assignors are typically the inventors.

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