WORD LINE DRIVER IN SEMICONDUCTOR MEMORY DEVICE USING A MAIN DECODER AND A PLURALITY OF MIDDLE AND SUB-DECODERS

A word line driver in a semiconductor memory device. The driver has first to (2.sup.m-n)th middle decoding units for commonly inputting an address signal of n bit and for outputting metal control signals by 2.sup.n so as to selectively drive 2.sup.m word lines by dividing them by 2.sup.n ; a main decoding unit for selectively driving the first to (m-n)bits th middle decoding units by an address signal of (m-n) bits; and first to (2.sup.m-n)th sub decoding units for commonly inputting a high voltage via a metal power line, and after coupled with 2.sup.n word lines of the 2.sup.m word lines of the cell array block, for selectively applying the high voltage to the 2.sup.n word lines to selectively drive them according to logic signals of 2.sup.n metal control lines, the first to (2.sup.m-n)th sub decoding units being coupled with the first to (2.sup.m-n)th middle decoding units and the 2.sup.n metal control lines, respectively.