EMITTER COUPLED LOGIC (ECL) GATE AND METHOD OF FORMING SAME

A fully differential, low voltage ECL gate (300) receives complementary logic signals (A, Ax, B, Bx) and provides them to first and second differential pairs (306, 318). Collectors from different differential pairs (306) and (318) are coupled together and provided with independent current paths through load resistors, R1, (336) and R2 (338). Differential outputs (OUT, OUTx) are generated at the common collector nodes (344, 346). The load resistors (336, 338) are selected to control the gain and ensure that a minimum switching threshold (V.sub.th) is maintained under all differential input signal conditions of (A, Ax, B, and Bx) for a logical AND or OR function.