IMPLEMENTATION OF HIGH SPEED SYNCHRONOUS STATE MACHINES WITH SHORT SETUP AND HOLD TIME SIGNALS

An apparatus and method of handling short setup and hold time input signals. The apparatus separates the processing of the data signals into an input flip-flop portion, a state machine portion, a combinatorial logic mapping portion and a rapid selecting circuit. The input flip-flops capture the signals allowing processing when the hold times are very small. The state machine portion generates a new current state from the input signals. The combinatorial logic mapping circuit generates a set of possible outcomes based on the result of the state machine and moderate setup time inputs. A rapid selecting circuit quickly chooses among the possible outcomes based on received short setup and hold time signals.