PARALLEL PROCESSOR WITH MEMORY/ALU INHIBITING FEATURE

A parallel processor comprises a data input register, a plurality of processor elements, a data output register, control means and instruction signal generating means. The data input register is for receiving a plurality of first data composed of serial data and outputting the first data as parallel data. The plurality of processor elements are for performing prescribed arithmetic operations on the first data as parallel data and outputting a plurality of arithmetically-processed second data. The data output register is provided with the plurality of second data as parallel, and outputs the second data as serial data. The control means jointly controls the operating states of the plurality of processor elements. The instruction signal generating means is for generating instruction signals instructing inhibiting of the prescribed arithmetic operations occurring at each of the processor elements on the basis of pre-defined arithmetic conditions for the prescribed arithmetic processes for the processor elements. Here, the prescribed arithmetic operations for the plurality of processor elements are inhibited in accordance with the instruction signals.