Patent №
US 5,880,985
Granted
1999-03-09
Filed 1996
Owner
INTEL CORPORATON
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
08735058
In order to multiply operands of different binary lengths using a common combined array, for example to do both 8 bit by 8 bit and 16 bit by 16 bit multiplications, 2.sup.m-1 multiplications are performed, where m is equal to the number of different bit lengths it is desired to multiply. For example, where 8.times.8 bit and 16.times.16 bit multiplications are done, 2 different multiplications are done. Each multiplication is an n.times.n/2.sup.m-1 multiplication, e.g., a 16.times.8 bit multiplication. Sign correction is performed by adding a correction vector or by modifying one of the partial products. The results of the multiplications are added together to obtain a 2 n bit result. Groups of bits from said 2 n result are selected depending on the length of the operands being multiplied.
AI classification
Ownership
INTEL CORPORATON
assignment · 83880430
Assignors
MAKINENI, SIVAKUMAR, HARRIS, DAVID, GRUTKOWSKI, THOMAS, MORRISON, MICHAEL J.
On an employer assignment, the assignors are typically the inventors.