SPLIT CAPACITOR ARRAY FOR DIGITAL-TO-ANALOG SIGNAL CONVERSION

A capacitor array-based, successive approximation analog-to-digital signal converter includes a capacitor array with a central coupling capacitor having a unit-value capacitance and two sets of input coupling capacitors having capacitances which are binary weighted multiples of such unit-value capacitance. During the sampling phase, the first set of input coupling capacitors is grounded while the second set of input coupling capacitors is driven by the analog input voltage. During the holding, or conversion, phase, one of the input coupling capacitors in the second set is grounded while each one of the input coupling capacitors in the first set and each one of the remaining input coupling capacitors in the second set is driven by a respective binary multiple of a fixed reference voltage, with each one of such binary multiples corresponding to one of the bits of the successive approximation result.