SYSTEM AND METHOD FOR BUS MASTER EMULATION

A system and method in accordance with the invention allows the emulation of a DMA transfer between a device such as a CD-ROM which is incapable of a bus-mastering mode of operation (e.g., a DMA transfer) and a memory. Following receipt of an interrupt request, a system in accordance with the invention generates an I/O access cycle to the device, retrieves data and stores the data in a buffer. Following data retrieval, the system transfers the data to host memory. Once data is transferred to host memory, an interrupt is generated to the host processor. Thus, host processor resources are not required to perform a data transfer with devices unable to become bus-masters.