Patent US 5,893,151

An apparatus for maintaining cache coherency for snoop operations includes a processor core for fetching, decoding, and executing instructions, a data cache coupled to the processor core for providing data to the processor core and for receiving data from the processor core, and a system bus coupling the processor core to the data cache. The apparatus further includes a snoop scheduler coupled to the processor core, the data cache, and the system bus, where the snoop scheduler is coupled to receive addresses from the system bus. The snoop scheduler also determines if snoop operations are orthogonal and schedules one or more out-of-order and at least partially overlapping snoop operations. Determining which snoop operations are orthogonal includes utilizing a block bit, a sleep bit, and a plurality of previously pending snoop request bits in a snoop queue entry to determine if the entry is orthogonal or not.