APPARATUS AND METHOD FOR AUTOMATICALLY PLACING TIES AND CONNECTION ELEMENTS WITHIN AN INTEGRATED CIRCUIT

Patent №

US 5,901,065

Granted

1999-05-04

Filed 1996

Owner

MOTOROLA, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

08597768

Methods (100, 200, 250) and data processing system (300) for automatically placing ties (136, 138, 146, 148) and connection elements within an integrated circuit (120). Integrated circuit dimensions (102), element locations and element dimensions (104), and tie placement rules (106) are received for a particular integrated circuit (120). The quantities are then processed to place ties within the integrated circuit (108). Tie placement rules include tie spacings (164, 166), well edge spacings (162), and diffusion spacings (168) to prevent SCR latch up and gate threshold voltage drift. Tie placement methods (100, 200) automatically place ties within the integrated circuit (120) to comply with tie spacing rules and also consider estimated compactions so that tie numbers are minimized. Associated data processing system (300) and computer readable medium operate in conjunction with the methods of the present invention. A method of making an integrated circuit (350) optimally places ties and connection elements within an integrated circuit design.

AI hardwareG06F 30/39G06Q 10/043H10D 84/854H10D 89/00

AI classification

AI hardware0.99
Machine learning0.13
Planning0.11
Vision0.05
Knowledge representation0.03
Natural language0.00
Evolutionary computation0.00
Speech0.00

Ownership

MOTOROLA, INC.

assignment · 78600082

Assignors

GURUSWAMY, MOHAN, DULITZ, DANIEL W., MAZIASZ, ROBERT

On an employer assignment, the assignors are typically the inventors.

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