MULTI-CHIP SUPERSCALAR MICROPROCESSOR MODULE

The pipeline of a microprocessor is partitioned near its mid point such that a first portion of the functionality of the microprocessor is implemented on a first integrated circuit chip and a second portion of the microprocessor functionality is implemented on a second integrated circuit chip. In one implementation, the first integrated circuit chip includes an instruction cache, an instruction alignment unit, and a plurality of decode units for implementing fetch, alignment and decode stages, respectively, of the processor pipeline. Instructions are selected from the instruction cache by the instruction alignment unit and are provided to a respective decode unit. A compression unit may compress the information output by the decode units to prepare conveyance of the information from the first integrated chip to the second integrated circuit chip. The second integrated circuit chip contains circuitry to implement execute and write-back stages of the processor pipeline. This circuitry may include a plurality of execution units coupled to receive output signals from the decoders of the first integrated circuit chip, corresponding reservation stations, a load/store unit and a data cache. A decompression unit may be coupled to receive the compressed information from the compression unit of the first integrated circuit chip to decompress the information prior to providing it to the reservation stations and/or execution units.