HOST PROCESSOR AND COPROCESSOR ARRANGEMENT FOR PROCESSING PLATFORM-INDEPENDENT CODE

A multiple processor circuit arrangement utilizes a host processor which controls the operational state of a coprocessor by programming internal control registers on the coprocessor. The host processor and coprocessor are coupled to an expansion bus, and the coprocessor is adapted to execute platform-independent code on behalf of the host processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as the coprocessor in the aforementioned host/coprocessor computer system, the coprocessor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is, effectively, native to the coprocessor.