TIMER WITH DYNAMIC RESET THRESHOLD

A timing vernier repeatedly generates a timing output signal, which includes a timing event such as a state transition, pulse, etc. Unlike prior timing verniers, the present timing event is capable of significantly faster repetition rates. After the ramp signal is initiated responsive to a trigger signal, it changes from a predetermined starting level at a predetermined substantially linear rate. A digital-to-analog converter (DAC) provides an analog timing select signal and a reset select signal responsive to a digital timing select signal. The reset select signal represents the current timing select signal offset by a predetermined amount. A comparator, coupled to the ramp and the DAC, produces the timing event when the ramp output signal reaches the analog timing select signal. Thus, greater analog timing select signals cause earlier timing events, whereas lesser timing select signals result in later timing events. The delay of the timing event is directly proportional to the analog timing select signal. A threshold sensor, coupled to the ramp and the DAC, provides the ramp's reset signal when the ramp output signal reaches the reset select signal. Since the reset select signal is automatically adjusted to be a fixed offset from the analog timing select signal, the ramp is reset as early as possible, without waiting for the ramp output signal to finish its course.