COMPUTER SYSTEM HAVING TAG INFORMATION IN A PROCESSOR AND CACHE MEMORY

The present invention includes a computer system having an on-processor predictor tag array, an off-processor cache memory, and comparison circuitry. The on-processor predictor tag array contains first portions of tag information for multiple ways and multiple sets. The off-processor cache memory includes memory locations to store data and second portions of tag information. The comparison circuitry makes a first comparison of a first portion of an address with the first portions of tag information for the ways of one of the sets and uses results of the first comparison in predicting which of the ways, if any, correspond to the address. The comparison circuitry also makes a second comparison of the second portion of the address with sections of the second portions of tag information identified by the predicted way and the address.