Patent US 5,963,979

A system for updating an inactive system memory includes a first package set in an active state and having a first processor and a second package set in an inactive state and having a second processor. The first package includes a first buffer memory, a first write control unit for outputting a write control signal and an address signal to the first buffer memory in accordance with a write control signal output from the first processor to the first memory, and a first holding unit for holding update data and an address signal output from the first processor to the first memory, and outputting held contents as data of the first buffer memory in accordance with a write control signal output from the first write control unit to the first buffer memory. The second package has the same arrangement as the first package. The second processor in an inactive state updates the second memory in accordance with update data and address data set for the first memory and stored in the first buffer memory.