SYSTEM AND MERTHOD FOR UNCACHED STORE BUFFERING IN A MICROPROCESSOR

In a microprocessor system utilizing a cache memory, an uncached store buffer is provided for efficiently providing uncached store data and uncached store addresses to a multiplexed system interface address/data bus. The uncached store buffer includes detector means, coupled to receive uncached store addresses, for detecting on-the-fly successive uncached store addresses which are identical, and for detecting on-the-fly successive uncached store addresses which are sequential. The uncached store buffer further includes an address buffer, coupled to receive and store a plurality of the uncached store addresses, and control logic, coupled to an output of the detector means, having a control signal. A data buffer, coupled to receive uncached store data, is further provided to store a plurality of blocks of the uncached store data. The uncached store data is arranged in the data buffer without gaps under the control of the control signal. Finally, an output multiplexer, having a first input coupled to an output of the address buffer, a second input coupled to an output of the data buffer, and an output coupled to the multiplexed system interface address/data bus, is provided to selectively issue the uncached store addresses and the uncached store data to the multiplexed system interface address/data bus.