DATA PROCESSING APPARATUS REGISTERS

A data processing system is provided including an arithmetic logic unit 20, 22, 24 receiving input operands from M X-bit registers to produce output data words stored within N Y-bit registers, where M/N=3, 8.ltoreq.Y-X.ltoreq.16 and 3X=2Y. This arrangement is particularly suited for digital signal processing and in situations where each input operand is used a plurality of times before a new input operand is loaded in its place in a register.