Patent №
US 5,986,313
Granted
1999-11-16
Filed 1997
Owner
PANASONIC CORPORATION
+2 more
Lab
—
AI components
1
ml
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
08988776
There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for ccntact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.
AI classification
Ownership
PANASONIC CORPORATION
namechg · 315060602
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
assignment · 315490818
RPX CORPORATION
assignment · 319390247
Assignors
UEDA, TETSUYA, UEHARA, TAKASHI, YANO, KOUSAKU, UEDA, SATOSHI
On an employer assignment, the assignors are typically the inventors.