CACHE MEMORY DEVICE AND METHOD FOR PROVIDING CONCURRENT INDEPENDENT MULTIPLE ACCESSES TO DIFFERENT SUBSETS WITHIN THE DEVICE

A multi-access method which is applied to a cache memory device interposed between a processor and a storage device, for enabling multi-access. When two or more access requests are received, a plurality of pairs (each pair composed of a data array and a tag array) are divided into two or more non-overlapping subsets, and each of the subsets is supplied with information which specifies data to be accessed and is input in conjunction with each access request, whereby accesses are performed in parallel in accordance with the access requests. This multi-access method is applicable to a cache memory used in a high-performance parallel-processing architecture including a few processors having a common cluster.